1. Field of the Invention
The present invention relates to a technique of distributing a clock signal to elements of a semiconductor integrated circuit, and particularly, to a method and apparatus for optimizing a depth of a tree network for clock distribution with minimal power consumption.
2. Description of the Prior Art
Improvements in semiconductor technology have developed large-scale, high-speed semiconductor integrated circuits. These circuits have many elements that must receive clock signals whose frequencies are increasing these days.
Synchronous systems realize correct operation timing on elements by synchronizing the operation timing in response to rising edges and falling edges of a clock signal. Ideally, all elements in a semiconductor integrated circuit which need a clock signal must receive it without delay. Actually, the clock signal received by the elements involves delay due to the resistance and capacitance of the metal lines used to distribute the clock signal to the elements. If two elements which are controlled by the same clock signal are at different distance from the clock root driver, they will receive the clock signal at different times. This arrival time differential is called skew. A large skew spoils synchronism in the operation of the elements, and therefore, the skew must be minimized by reducing the delay.
An H-tree network for distributing a clock signal to elements of a semiconductor integrated circuit was proposed by S. Dhar et al in "Reduction of clock delays in VLSI structures," Proc. IEEE Int. Conf. on Computer Design, 1984. Improved H-tree networks are disclosed in Japanese Patent Application Publication Nos. 3-030721 and 3-137851.
The H-tree networks usually employ multistage buffering to reduce delay in distributing a clock signal. The multistage buffering arranges buffer cells at nodes in several stages of an H-tree network in a semiconductor integrated circuit, so that a clock signal is distributed from a root driver to elements of the integrated circuit through the buffer cells. In the multistage buffering, first-stage buffer cells drive second-stage buffer cells, the second-stage buffer cells drive third stage buffer cells, and so on. Last-stage buffer cells directly drive each of the elements which are grouped. Each group contains at least one of elements. In each group of elements, no H-tree is formed, and the elements are connected to one another through shortest wiring. Such a group of elements is sometimes called a "cluster."
However, the prior arts mentioned above give no consideration on power consumption of an H-tree networks.
To reduce power consumption of a clock distribution network, J. Cong et al proposed a technique of optimizing the size of buffer cells, i.e., the gate length and width of each CMOS transistor, or the width of the metal lines that carry the clock signal to the elements, in "Simultaneous Driver and Wire Sizing for Performance and Power Optimization," Proc. IEEE Int. Conf. on CAD, 1994. The objective of this prior art, however, is an H-tree network without multistage buffering, and therefore, the prior art is inapplicable to H-tree networks employing multistage buffering.